?2004 fairchild semiconductor corporation rfD14N05L, rfD14N05Lsm, rfp14n05l rev. b1 rfD14N05L, rfd14n 05lsm, rfp14n05l 14a, 50v, 0.100 ohm, logic level, n-channel power mosfets these are n-channel power mosfets manufactured using the megafet process. this process, which uses feature sizes approaching those of lsi integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. they were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. this performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3v-5v range, thereby facilitating true on-off power control directly from logic level (5v) integrated circuits. formerly developmental type ta09870. features ? 14a, 50v r ds(on) = 0.100 ? temperature compensating pspice ? model can be driven directly from cmos, nmos, and ttl circuits peak current vs pulse width curve uis rating curve 175 o c operating temperature related literature - tb334 ?guidelines for soldering surface mount components to pc boards? symbol packaging jedec to-251aa jedec to-252aa jedec to-220ab ordering information part number package brand rfD14N05L to-251aa 14n05l rfD14N05Lsm to-252aa 14n05l rfp14n05l to-220ab f14n05l note: when ordering, use the entire part number. add the suffix 9a to obtain the to-252aa variant in the tape and reel, i.e., rfD14N05Lsm9a. g d s source drain (flange) gate drain gate source drain (flange) gate drain (flange) source drain data sheet november 2004
?2004 fairchild semiconductor corporation rfD14N05L, rfD14N05Lsm, rfp14n05l rev. b1 absolute maximum ratings t c = 25 o c, unless otherwise specified rfD14N05L, rfD14N05Lsm, rfp14n05l units drain to source voltage (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 50 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 50 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 10 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i d pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 14 refer to peak current curve a pulsed avalanche rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as refer to uis curve power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 0.32 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j, t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t pkg 300 260 o c o c caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. t j = 25 o c to 150 o c. electrical specifications t c = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v, figure 13 50 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 250 a, figure12 1 - 2 v zero gate voltage drain current i dss v ds = 40v, v gs = 0v - - 1 a v ds = 40v, v gs = 0v, t c = 150 o c--50 a gate to source leakage current i gss v gs = 10v - - 100 na drain to source on resistance (note 2) r ds(on) i d = 14a, v gs = 5v, figures 9, 11 - - 0.100 ? turn-on time t (on) v dd = 25v, i d = 7a, r l = 3.57 ? , v gs = 5v, r gs = 0.6 ? --60ns turn-on delay time t d(on) -13 - ns rise time t r -24 - ns turn-off delay time t d(off) -42 - ns fall time t f -16 - ns turn-off time t (off) - - 100 ns total gate charge q g(tot) v gs = 0v to 10v v dd = 40v, i d = 14a, r l = 2.86 ? figures 20, 21 - - 40 nc gate charge at 5v q g(5) v gs = 0v to 5v - - 25 nc threshold gate charge q g(th) v gs = 0v to 1v - - 1.5 nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz figure 14 - 670 - pf output capacitance c oss - 185 - pf reverse transfer capacitance c rss -50 - pf thermal resistance junction to case r jc - - 3.125 o c/w thermal resistance junction to ambient r ja to-251 and to-252 - - 100 o c/w r ja to-220 - - 80 o c/w source to drain diode specifications parameter symbol test conditions min typ max units source to drain diode voltage (note 2) v sd i sd = 14a - - 1.5 v diode reverse recovery time t rr i sd = 14a, di sd /dt = 100a/ s - - 125 ns notes: 2. pulse test: pulse width 300ms, duty cycle 2%. 3. repetitive rating: pulse width limited by max junction temperature. see transient thermal impedance curve (figure 3) and peak current capability curve (figure 5). rfD14N05L, rfD14N05Lsm, rfp14n05l
?2004 fairchild semiconductor corporation rfD14N05L, rfD14N05Lsm, rfp14n05l rev. b1 typical performance curves unless otherwise specified figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs temperature figure 3. normalized maximum transient thermal impedance figure 4. forward bias safe operatin g area figure 5. peak current capability t c , case temperature ( o c) 25 50 75 100 125 150 17 5 0 power dissipation multiplier 0 0 0.2 0.4 0.6 0.8 1.0 1.2 8 4 0 25 50 75 100 125 150 12 i d , drain current (a) t c , case temperature ( o c) 16 17 5 t, rectangular pulse duration (s) 10 -3 10 -2 10 -1 10 0 0.01 0.1 1 10 -5 10 1 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 0.5 10 -4 2 thermal impedance z jc , normalized v ds , drain to source voltage (v) 10 10 0 1 100 10 1 i d , drain current (a) dc 100 s 100ms 1ms 10ms 0.5 limited by r ds(on) area may be operation in this t c = 25 o c t j = max. rated t, pulse width (s) 10 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 v gs = 10v 100 i dm , peak current capability (a) transconductance may limit current in this region i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: v gs = 5v 200 t c = 25 o c rfD14N05L, rfD14N05Lsm, rfp14n05l
?2004 fairchild semiconductor corporation rfD14N05L, rfD14N05Lsm, rfp14n05l rev. b1 note: refer to fairchild application notes an9321 and an9322. figure 6. unclamped inductive switching figure 7. saturation characteristics figure 8. transfer characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. switching time vs gate resistance figure 11. normalized drain to source on resistance vs junction temperature typical performance curves unless otherwise specified (continued) 0.1 1 1 0 10 0.01 50 1 t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss -v dd ) +1] i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c 0 5 10 15 0 1.5 3.0 4.5 7. 5 20 25 i d , drain current (a) v ds , drain to source voltage (v) v gs = 4v v gs = 10v 30 35 6.0 v gs = 3v v gs = 2.5v v gs = 5v v gs = 4.5v pulse duration = 80 s, t c = 25 o c duty cycle = 0.5% max. 03.04.56.07. 5 1.5 0 5 10 15 20 25 175 o c i ds(on) , drain to source current (a) v gs , gate to source voltage (v) -55 o c 30 35 25 o c pulse duration = 80 s duty cycle = 0.5% max. v dd = 15v 0 50 100 150 200 2.5 3.0 3.5 4.0 4.5 r ds(on) , drain to source v gs , gate to source voltage (v) 5. 0 250 i d = 28a i d = 7a i d = 3.5a i d = 14a pulse duration = 80 s duty cycle = 0.5% max. on resistance (m ? ) 0 20 010 20 30 40 switching time (ns) r gs , gate to source resistance ( ? ) 5 0 40 60 80 100 120 140 160 t d(off) t r t f t d(on) v dd = 25v, i d = 14a, r l = 3.57 ? 0 0.5 1.0 1.5 2.0 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) 20 0 2.5 pulse duration = 80 s on resistance v gs = 10v, i d = 14a duty cycle = 0.5% max. rfD14N05L, rfD14N05Lsm, rfp14n05l
?2004 fairchild semiconductor corporation rfD14N05L, rfD14N05Lsm, rfp14n05l rev. b1 figure 12. normalized gate threshold voltage vs junction temperature figure 13. normalized drain to source breakdown voltage vs junction temperature figure 14. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an7260, figure 15. transconductance vs drain current test circuits and waveforms figure 16. unclamped energy test circuit figure 17. unclamped energy waveforms typical performance curves unless otherwise specified (continued) -80 -40 0 40 80 120 160 0 0.5 1.0 1.5 2.0 normalized gate threshold voltage t j , junction temperature ( o c) 20 0 v gs = v ds , i d = 250 a 2.0 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source breakdown voltage 20 0 i d = 250 a 800 200 0 0 5 10 15 20 2 5 c, capacitance (pf) 400 v ds , drain to source voltage (v) c iss c oss c rss 600 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd 40 30 20 10 0 20 i gref () i g act () ------------------------ - t, time ( s) 80 i gref () i gact () ------------------------ - 5 3 2 1 0 v dd = bv dss v dd = bv dss v ds , drain to source voltage (v) v gs , gate to source voltage (v) r l = 3.57 ? i g(ref) = 0.4ma v gs = 5v 0.75 bv dss 0.50 bv dss 0.25 bv dss 50 4 t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 rfD14N05L, rfD14N05Lsm, rfp14n05l
?2004 fairchild semiconductor corporation rfD14N05L, rfD14N05Lsm, rfp14n05l rev. b1 figure 18. switching time test circui t figure 19. resistive switching waveforms figure 20. gate charge test circuit figure 21. gate charge waveforms test circuits and waveforms (continued) v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(5) v gs = 5v q g(tot) v gs = 10 v v ds v gs i g(ref) 0 0 rfD14N05L, rfD14N05Lsm, rfp14n05l
?2004 fairchild semiconductor corporation rfD14N05L, rfD14N05Lsm, rfp14n05l rev. b1 pspice electrical model .subckt rfp14n05l 2 1 3 ; rev 9/15/94 ca 12 8 1.464e-9 cb 15 14 1.64e-9 cin 6 8 6.17e-10 dbody 7 5 dbdmod dbreak 5 11 dbkmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 65.35 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evto 20 6 18 8 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 5.68e-9 lsource 3 7 5.35e-9 mos1 16 6 8 8 mosmod m = 0.99 mos2 16 21 8 8 mosmod m = 0.01 rbreak 17 18 rbkmod 1 rdrain 50 16 rdsmod 33.1e-3 rgate 9 20 5.85 rin 6 8 1e9 rscl1 5 51 rsclmod 1e-6 rscl2 5 50 1e3 rsource 8 7 rdsmod 14.3e-3 rvto 18 19 rvtomod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 8 19 dc 1 vto 21 6 0.485 escl 51 50 value = {(v(5,51)/abs( v(5,51)))*(pwr(v(5,51)*1e6/46,7))} .model dbdmod d (is = 2.23e-13 rs = 1.15e-2 trs1 = 1.64e-3 trs2 = 7.89e-6 cjo = 6.83e-10 tt = 3.68e-8) .model dbkmod d (rs = 3.8e-1 trs1 = 1.89e-3 trs2 = 1.13e-5) .model dplcapmod d (cjo = 25.7e-11 is = 1e-30 n = 10) .model mosmod nmos (vto = 1.935 kp = 18.89 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model rbkmod res (tc1 = 7.18e-4 tc2 = 1.53e-6) .model rdsmod res (tc1 = 4.45e-3 tc2 = 2.9e-5) .model rsclmod res (tc1 = 2.8e-3 tc2 = 6.0e-6) .model rvtomod res (tc1 = -1.7e-3 tc2 = -2.0e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -3.55 voff= -1.55) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -1.55 voff= -3.55) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -2.55 voff= 2.45) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 2.45 voff= -2.55) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; authored by william j. hepp and c. frank wheatley. 1 gate lgate rgate evto 18 8 + 12 13 8 14 13 13 15 s1a s1b s2a s2b ca cb egs eds rin cin mos1 mos2 dbreak ebreak dbody ldrain drain rsource lsource source rbreak rvto vbat it vto esg dplcap 6 6 8 10 5 16 21 11 17 18 8 14 5 8 6 8 7 3 17 18 19 2 + + + + + + 20 rdrain escl rscl1 rscl2 51 50 5 51 + 9 rfD14N05L, rfD14N05Lsm, rfp14n05l
disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production isoplanar? littlefet? microcoupler? microfet? micropak? microwire? msx? msxpro? ocx? ocxpro? optologic ? optoplanar? pacman? pop? fast ? fastr? fps? frfet? globaloptoisolator? gto? hisec? i 2 c? i-lo ? implieddisconnect? rev. i13 acex? activearray? bottomless? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? fact? fact quiet series? power247? poweredge? powersaver? powertrench ? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? serdes? silent switcher ? smart start? spm? stealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic ? tinyopto? trutranslation? uhc? ultrafet ? vcx? across the board. around the world.? the power franchise ? programmable active droop?
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